1. Field of the Invention
The present invention relates to a method of forming a MOS transistor, and more particularly, to a method of forming a gate of the MOS transistor and a landing pad on the drain and source of the MOS transistor at the same time.
2. Description of the Prior Art
A memory cell of dynamic random access memory (DRAM) is formed by a metal oxide semiconductor (MOS) transistor, a capacitor and a node contact. The MOS transistor is used as a pass transistor of the memory cell to control the flow of charge. The capacitor is used to store the charge required for recording and recalling data. The node contact is used as a contact plug for electrically connecting the MOS transistor and the capacitor.
Please refer to FIG. 1 and FIG. 2. FIG. 1 and FIG. 2 are schematic diagrams of a method of forming a MOS transistor 25 according to the prior art. The prior art MOS transistor 25 is formed on a silicon substrate 12 of a semiconductor wafer 10. As shown in FIG. 1, a silicon oxide layer 14 is first formed on the silicon substrate 12. Then, at least one gate 16 is formed on a predetermined area of the silicon oxide layer 14. Next, an ion implantation process is performed to form two doping areas 20 in the silicon substrate 12 on two opposite sides of the polysilicon layer 16 wherein each of the two doping areas 20 is used as a lightly doped drain (LDD) of the MOS transistor 25.
Next, as shown in FIG. 2, a spacer 22 made of silicon nitride is formed around the periphery of each polysilicon layer 16. Then, an ion implantation process is performed to form two heavy doping areas 24 in the silicon substrate 12 on the two opposite sides of the spacer 22 so as to complete the MOS transistor 25. Each of the two heavy doping areas 24 is used as a drain or a source 24 of the MOS transistor 25.
However, when the pattern of semiconductor devices is reduced, it becomes more difficult to form a node contact of the DRAM using only etching and deposition processes. Therefore, in current semiconductor processing, a landing pad and another contact plug are formed to serve as the base for a shorter node contact. Forming this contact plug and landing pad prior to the formation of the shorter node contact decreases the difficulty in the whole node contact process and further ensures the electrical performance of the DRAM.
Please refer to FIG. 3 to FIG. 7. FIG. 3 to FIG. 7 are schematic diagrams of a method of forming a landing pad 38 on the semiconductor wafer 10 shown in FIG. 2. When the MOS transistor 25 is completed, a landing pad 38 can be formed on the drain or source 24. As shown in FIG. 3, a dielectric layer 26 made of silicon oxide is first formed on the semiconductor wafer 10. Then a lithographic process is performed to form a first photoresist layer 28 on the dielectric layer 26 wherein the first photoresist layer 28 comprises an opening 30 to the surface of the dielectric layer 26. Next, as shown in FIG. 4, an anisotropic etching process is performed to remove the dielectric layer 26 under the opening 30 so as to form a contact hole 32. Then, a stripping process is performed to completely remove the first photoresist layer 28.
Next, as shown in FIG. 5, a conductive layer 34 is uniformly formed on the semiconductor wafer 10 and fills the contact hole 32. Then, as shown in FIG. 6, a second photoresist layer 36 is formed on a predetermined area of the conductive layer 34 for defining the position of the landing pad 38. Finally, as shown in FIG. 7, the conductive layer 34 not covered by the second photoresist layer 36 is removed, and then the photoresist layer 36 is also removed. The top end of the conductive layer 34 protruding from the dielectric layer 26 is used as the landing pad 38 for electrically connecting a sequentially formed storage node of a capacitor. The pillar-shaped portion at the bottom of the conductive layer 34 is used as a contact plug 37 for electrically connecting the drain and source 24 positioned on the silicon substrate 12.
The formation of the MOS transistor 25 is prior to the formation of the landing pad 38 and the contact plug 37 within the contact hole 32. However, it is difficult to control the etching selection ratio of silicon nitride to silicon oxide when the etching process is performed along the opening 30 on the dielectric layer 26 to form the contact hole 32. If the position of the opening 30 is not exactly defined, the surface of the gate 16 and the spacer 22 can easily be etched, with the result that the subsequently formed contact plug 37 is too close to the gate 16, causing electrical coupling effects. Therefore, the lithographic process must be exactingly controlled when forming the opening 30 of the first photoresist layer 28 to precisely define the position of the contact hole 37, thereby ensuring the electrical performance of the DRAM. Furthermore, the lithographic process must be performed again to form the second photoresist layer 36 on the conductive layer 34 for exactly defining the position of the landing pad 30. It is believed that the whole DRAM process is too complex.